The present invention relates generally to the testing of electronic memory devices, and in particular, the present invention relates to testing of Direct Rambus Dynamic Random Access Memory (DRDRAM).
Direct Rambus Dynamic Random Access Memories, hereinafter referred to as DRDRAMs, are very fast, highly pipelined memory devices that are becoming an industry standard in high speed processing systems. DRDRAMs include a considerable amount of internal circuitry that supports the pipelined architecture so as to provide for very high communication bandwidths at the device boundary. DRDRAM sustained data transfer rates exceed 1 GB/s.
DRDRAMs, like most commercially available memories, include memory cells that are arranged in rows and columns. Unlike many commercially available memories, however, DRDRAMs have rows gathered into banks of rows. This results in multiple banks within each DRDRAM, each including a number of rows. Gathering the rows of memory cells into banks allows rows in different banks to undergo separate operations simultaneously, thereby increasing the overall data transfer rate of the device.
Each bank is associated with one or more sense amplifiers that function to read data from, and write data to, the rows within the bank. The sense amplifiers serve as a data communications bridge between the banks of rows and the data buses external to the device. Banks are separately activated, possibly simultaneously, or overlapping in time, prior to a read or write operation. When a bank is activated, it communicates with one or more sense amplifiers. When the read or write operation is complete, the bank is deactivated, and the sense amplifiers are precharged, which essentially readies the sense amplifiers for another operation.
DRDRAMs include internal circuitry that controls, among other things, the data communication between banks and sense amplifiers, and the data communication between sense amplifiers and external data buses. The data communication between banks and sense amplifiers is generally controlled by a row decoder that is responsive to xe2x80x9crow packetsxe2x80x9d received by the DRDRAM. The data communication between the sense amplifiers and external data buses is generally controlled by a column decoder that is responsive to xe2x80x9ccolumn packets.xe2x80x9d
A typical DRDRAM access is a multistep process. A bank and row is specified by a row command in a row packet, and then a column within the row is specified using a column command in a column packet. The sense amplifiers respond to the row command by copying the contents of the specified row from the activated bank into the sense amplifiers, and then respond to the column command by either: sending data to the external bus in the case of a read operation; or modifying the contents of the specified row in the activated bank in the case of a write operation.
DRDRAMs also have reduced power states. These states shut down portions of the device to save power. In the reduced power states, the contents of the memory array are saved, but other functions within the DRDRAM are shut down to conserve power. One such reduced power state is the Standby (STBY) state, in which the column decoder is shut down. When in STBY, the DRDRAM is ready to receive row packets, but will properly ignore any column packets received. DRDRAMs are put in STBY when given a relax (RLX) command in a row or column packet. Banks can be active when the RLX command is given (and the device is put in STBY), but this is not a likely usage pattern because this would put the device in STBY in the middle of an operation, and the purpose of the STBY state is to conserve power between operations. It is much more likely that the DRDRAM will have no banks active when the RLX command is given, because this will put the DRDRAM in STBY between operations rather than in the middle of an operation. This type of STBY state usage is clearly intended, as stated in the xe2x80x9cRambus Direct RDRAM 128/144-Mbit (256kx16/18x32s) Preliminary Information,xe2x80x9d Document DL0059, V1.0, May 1999, at page 39. The contents of the aforementioned document, which is hereinafter referred to as the xe2x80x9cDRDRAM Specification,xe2x80x9d is hereby incorporated by reference.
When testing the proper operation of reduced power states in a DRDRAM, the test can include operations to verify that portions of the device that are supposed to be shut down in a given state are, in fact, shut down. In the case of the STBY state, the test can verify that the column decoder is shut down. One method of testing that the column decoder is shut down in the STBY state involves issuing a RLX command while a bank is active, performing a read operation, and checking to make sure that the data output from the DRDRAM is all zero. A data read operation resulting in all zeros is indicative of the column decoder being shut down because the sense amplifiers have been loaded by virtue of the active bank, but the sense amplifiers have not driven the data bus. If the column decoder was not shut down, a proper read operation would result in non-zero data being output.
One problem with this method of testing the STBY state is that a bank remains active during the test, which is not the normal usage of the device. As previously discussed, normal STBY usage of the part, as recommended in the DRDRAM specification, involves issuing a RLX command while the part has no active banks.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and apparatus for testing memory devices having reduced power states.
The above mentioned problems with proper DRDRAM testing and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method in a processing system that includes a memory device is described. The memory device has a row decoder, a column decoder, and rows and columns of memory cells. The method tests for the proper operation of a reduced power state in the memory device. The method includes issuing a first command adapted to cause the memory device to enter the reduced power state, wherein the command is decoded by one of the row decoder or the column decoder; issuing a second command to the memory device, wherein the second command is directed to the column decoder; and comparing a data value returned by the memory device against an expected value to verify that the column decoder did not decode the second command.
A computer-implemented method for testing a memory device is also described. The method includes generating a command adapted to cause the memory device to enter a reduced power state; driving the command onto a first control bus; generating a calibration sequence which includes at least one current calibration packet, wherein the at least one current calibration packet is adapted to cause the memory device to output a data value; driving a second control bus with the at least one current calibration packet; and comparing the data value with an expected value.
In another embodiment, an apparatus for testing a memory device having multiple banks is described. The memory device tester includes a control bus for coupling to the memory device, a data bus for coupling to the memory device, and a state machine coupled to the control bus. The state machine is configured to output commands on the control bus, and at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active.
In another embodiment, an apparatus including a memory device having multiple banks is described. The apparatus further includes a control bus for coupling to the memory device, a data bus for coupling to the memory device, and a state machine coupled to the control bus. The state machine is configured to output commands on the control bus, and at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active.
In another embodiment, a memory device tester is described. The memory device tester includes a receptacle for receiving a memory device, a control bus coupled to the receptacle for communicating with the memory device, and a processing unit coupled to the control bus for sending commands to the memory device. The commands sent to the memory device include a first command adapted to cause the memory device to enter a reduced power state, a first current calibration sequence including at least one current calibration (CAL) command, a second command adapted to cause the memory device to leave the reduced power state, and a second current calibration sequence including at least one current calibration (CAL) command.
In yet another embodiment, a memory interface for inclusion in an Application Specific Integrated Circuit (ASIC) is described. The memory interface includes a control bus for coupling to a memory device external to the ASIC, wherein the memory device includes banks of memory cells capable of being active or inactive. The memory interface also includes a data bus for coupling to the memory device and a state machine coupled to the control bus. The state machine is configured to output commands on the control bus, wherein at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active.
In yet another embodiment, a machine readable medium is described. The medium is readable by an apparatus configured to test a memory device, and the machine readable medium includes instructions adapted to cause the apparatus to perform a method. The method includes generating a command within a first packet, wherein the command is adapted to cause the memory device to enter a reduced power state; driving a first control bus with the first packet; generating a calibration sequence within at least one current calibration packet, wherein the current calibration packet is adapted to cause the memory device to output a data value; driving a second control bus with the at least one current calibration packet; and comparing the data value with an expected value.